The present invention relates to the basic structure and the entire structure of a data processing apparatus including a semiconductor memory device, and specifically, to a data processing structure which internally operates and stores data in itself, a data processing structure unit consisting of a plurality of data processing units which transfer data to make interaction with each other, and a data processing structure represented by a semiconductor memory device consisting of the data processing unit or data processing structure unit.
Recently, data processing apparatuses represented by image data processing, data memory or the like have been developed and available as products. For example, semiconductor memory devices such as a dynamic random access memory (DRAM), a static random access memory (SDRAM), and the like have already been subjected to mass-production and used so as to comply with various specifications. In these data processing apparatuses, it is a basic principle that data to be read out ,is perfectly the same as data to be written, and there originally is a lack of an idea of making any operation processing on data to be written.
In this respect, a proposal has been made as to a concept for modifying a kind of dispersed data processing system into a device, i.e., cells utilizing a quantum phenomenon are realized and disposed as operation factors in a matrix-like array and the cells are caused to make close interactions between each other in accordance with rules set in compliance with purposes (Amamiya Yoshihito and Akazawa Masamichi, xe2x80x9cHow a quantum phenomenon should be combined with data processing to prepare a LSI with a quantum effect devicexe2x80x9d, Applied Physics, Vol. 64, No. 8, pages 765 to 768). In a device realized by the concept, for example, when four adjacent cells are xe2x80x9c1xe2x80x9d where a center cell surrounded by eight cells is xe2x80x9c1xe2x80x9d, the center cell is next changed to xe2x80x9c0xe2x80x9d in a step. When two adjacent cells are xe2x80x9c1xe2x80x9d, the state of xe2x80x9c1xe2x80x9d is maintained. Where the center cell is xe2x80x9c0xe2x80x9d, the center cell is not changed to xe2x80x9c1xe2x80x9d even when two adjacent cells are xe2x80x9c2xe2x80x9d. Thus, it is said that a change of the state of the center cell and further a change of data in a device can be realized.
However, in the prior art example described above, only an extremely conceptual instruction can be found with respect to realization of a device of a dispersed data processing system. Therefore, in consideration of a specific device, there is a problem as to what will be the form at the level of a device.
The present invention has been made to a situation as described above and has an object of providing a technique of realizing a kind of dispersed data processing system at the level of device, e.g., a special data processing unit or memory structure unit which realizes the technique, a data processing structure unit constructed by providing a plurality of said data processing units, the data processing unit, or a data processing structure comprising the data processing structure unit and a semiconductor memory device comprising the memory structure unit.
A data processing unit according to the present invention basically comprises: input for inputting first data from outside; an operation circuit for operating the first data to generate second data; memory for storing the second data; output for outputting the second data stored in the memory to the outside; and a controller for controlling the memory to enable storing and outputting of the second data.
The data processing unit may comprise a data reproduction circuit for reproducing the second data outputted. Further, the data processing unit may comprise a write circuit which is for inputting third data from the outside and writes the third data as the second data into the memory, and a read circuit for reading data stored in the memory. The operation circuit of the data processing unit may be a logic circuit among a group of logic circuits consisting of an identity logic circuit, an inversion logic circuit, an exclusive OR circuit, an exclusive AND circuit, an OR circuit, and an AND circuit, and may comprise at least two logic circuits among a group of logic circuits consisting of an identity logic circuit, an inversion logic circuit, an exclusive OR circuit, an exclusive AND circuit, an OR circuit, and an AND circuit, and a selector for selecting one output from outputs of the at least two logic circuits.
A first data processing structure unit according to the present invention is a dimer-like structure unit consisting of two data processing units each described above, in which the output of one data processing unit is electrically connected with the input of the other data processing unit. Further it is preferred that the two data processing units are arranged adjacent to each other.
A second data processing structure unit according to the present invention is a dimer-like structure unit consisting of first, second, and third data processing units as described above, in which the output of the first data processing unit is electrically connected with the input of the second data processing unit, and the output of the second data processing unit is electrically connected with the input of the third data processing unit. In this trimer-like data processing structure unit, it is preferred that the first and second data processing units, as well as the second and third data processing units, are arranged adjacent to each other.
A first data processing structure according to the present invention is a structure comprising a plurality of data processing units as described above, in which the first data of each data processing unit is one or two or more data items, and all or a part thereof is the second data outputted from the output of other one or two or more data processing units. The first data processing structure preferably comprises connection circuits for electrically connecting the input of each of the data processing units with the output of a data processing unit other than the data processing units itself.
A second data processing structure according to the present invention comprises two dimer-like data processing structure units each described above, and connection circuits for electrically connecting a first or second data processing unit of one of the data processing structure units with a first or second data processing unit in the other data processing structure unit.
A third data processing structure according to the present invention comprises two trimer-like data processing structure units each described above, and connection circuits for electrically connecting a first, second, or third data processing unit of one of the data processing structure units with a first, second, or third data processing unit in the other data processing structure unit.
In the second and third data processing structures constructed by a polymer-like data processing structure unit including the dimer-like and trimer-like units, it is preferred that two data processing structure units are arranged adjacent to each other, like an array. Where these data processing structures comprise a plurality of bit lines and a plurality of word lines crossing the bit lines, it is preferred that the data processing units in the data processing structure unit are provided at a cross-position between the bit lines and the word lines.
A fourth data processing structure according to the present invention comprises a plurality of data processing units, and each of the data processing units comprises: an operation circuit for operating on first data inputted from other one or two or more data processing units, by one of a group of logic operations consisting of identity, inversion, exclusive OR, OR, and AND, to generate second data; memory for storing the second data; output for outputting the second data stored in the memory to one or two or more other data processing units than each of the data processing units itself; and a controller for controlling the memory to enable storing and outputting of the second data.
A fifth data processing structure according to the present invention comprises a plurality of data processing units, and each of the data processing units includes: an operation circuit for operating on first data inputted from one or two or more other data processing units than the data processing unit itself, by at least two of a group of logic operations consisting of identity, inversion, exclusive OR, OR, and AND, and for selecting one of operation results thereof, as second data; memory for storing the second data; output for outputting the second data stored in the memory to one or two or more other data processing units than the data processing unit itself; and a controller for controlling the memory to enable storing and outputting of the second data.
The fourth and fifth data processing structures may further comprise a reproduction circuit for reproducing second data in the memory, a write circuit for inputting third data from the outside of the data processing unit and for writing the third data as second data, or a read circuit for reading data stored in the memory.
In a sixth data processing structure according to the present invention, a first region occupied by a data processing unit comprising a write circuit for inputting third data from the outside and for writing the third data as second data into memory, and a read circuit for reading data stored in the memory, and a second region occupied by a data processing unit which does not comprise such write and read circuits are image-assigned (images are allocated to that region), and connection circuits for electrically connecting output and input of one or two or more data processing units in the first and second regions with each other is comprised.
A first semiconductor memory device according to the present invention consists of a plurality of bit lines, a plurality of word lines, and first and second memory structure units provided at a cross-position between the bit lines and the word lines, wherein each of the first and second memory structure units comprises input for inputting first data from outside, an operation circuit for operating on the first data inputted from the input to generate second data, memory for storing the second data, output for outputting the second data stored in the memory to the outside, a controller for controlling the memory to enable storing and outputting of the second data, a switch circuit by which connection and disconnection between the memory and a bit line are controlled by a word line, and a connection circuit for electrically connecting the input of the first memory structure unit and the output of the second memory structure unit with each other.
A second semiconductor memory device according to the present invention consists of a plurality of bit lines, a plurality of word lines, and first, second, and third memory structure units provided at a cross-position between the bit lines and the word lines, wherein each of the first, second, and third memory structure units comprises input for inputting first data from outside, an operation circuit for operating the first data inputted from the input to generate second data, memory for storing the second data, output for outputting the second data stored in the memory to the outside, a controller for controlling the memory to enable storing and outputting of the second data, a switch circuit by which connection and disconnection between the memory and a bit line are controlled by a word line, and a connection circuit for electrically connecting the input of the first memory structure unit and the output of the second memory structure unit with each other, as well as the input of the second memory structure unit and the output of the third memory structure unit with each other. In this case, it is preferred that the first and second memory structure units as well as the second and third memory structure units are adjacent to each other.
A third semiconductor memory device according to the present invention consists of a plurality of bit lines, a plurality of word lines, and a plurality of memory structure units provided at a cross-position between the bit lines and the word lines, wherein each of the memory structure units comprises a plurality of input terminals for inputting a plurality of first data items from outside, a plurality of operation circuits for operating on the plurality of first data items inputted from the plurality of input terminals to generate second data, memory for storing the second data, an output terminal for outputting the second data stored in the memory to the outside, a controller for controlling the memory to enable storing and outputting of the second data, a switch circuit by which connection and disconnection between the memory and a bit line are controlled by a word line, and a connection circuit for electrically connecting the plurality of input terminals of each of the memory structure units itself with the output terminals of the plurality of memory structure units adjacent to each of the memory structure units itself such that the input terminals of each of the memory structure units correspond to the output terminals of the plurality of memory structure units adjacent to each of the memory structure units itself.
Note that the operation circuit in the memory structure unit of the first to third semiconductor memory devices may be a logic operation circuit for operating on the first data by one of a group of logic operations consisting of identity, inversion, exclusive OR, OR, and AND, to generate the second data, or may comprise a logic operation circuit for operating the first data by at least two of a group of logic operations consisting of identity, inversion, exclusive OR, OR, and AND, and a selector for selecting one of operation results from the logic operation circuit, as the second data.
According to the present invention, a data processing unit itself, represented by a memory structure unit or a memory cell, is capable of autonomously operating on data from the outside, updating and storing a result thereof, and outputting it to the outside (hereinafter, this kind of function of data processing in the data processing unit will be called an xe2x80x9cautonomous data processing functionxe2x80x9d). Therefore, it is possible to realize a unit which interacts with the outside, and as a result, it is possible to realize dispersed data processing in the relationship between the outside and the data processing unit. The xe2x80x9coutsidexe2x80x9d used herein means an environment other than the data processing unit. Therefore, the xe2x80x9coutsidexe2x80x9d naturally includes all of another data processing unit, a data processing section (including a clock circuit) other than the data processing unit itself, incorporated in a data processing structure such as a semiconductor memory device including the data processing unit itself, or the outside of the data processing structure, and the like. However, it should be noted that an identity logic operation as a kind of operation process is included in case where data outputted to the outside from the data processing unit itself through an output is taken in as data from the xe2x80x9coutsidexe2x80x9d and subjected again to the autonomous data processing in the processing unit itself.
Although the data processing unit can be arranged so as to perform only the autonomous data processing function as described above, the data processing unit can be arranged so as to perform a basic data storing function which enables writing/reading of data by address-designation, like in case of a memory cell in a known semiconductor memory device (hereinafter, this kind of function is called a xe2x80x9cbasic data processing functionxe2x80x9d).
Further, the controller which controls the memory to enable storing and outputting of data is preferably a means for supplying a control command to the memory from the outside, in consideration of a physical request for downsizing the area of the data processing unit. In this case, the xe2x80x9coutsidexe2x80x9d may be an internal section of a data processing structure including the data processing unit itself or an external section thereof. In addition, an embodiment of the controller may be a control circuit which is incorporated separately in a data processing structure including the data processing unit itself and which is controlled by a signal from the outside of the data processing structure and supplies a control command to the memory.
In addition, according to the present invention, it is possible to realize a dimer like data processing structure unit consisting of two processing units which interact with each other and a trimer-like data processing structure unit consisting of three processing units which interact with each other. However, it is naturally possible to constitute a tetramer-like or higher data processing structure unit by arbitrarily combining a single processing unit and dimer-like and trimer-like data processing units with each other. A polymer-like data processing structure unit can be realized by electrically connecting a plurality of data processing units. In this kind of data processing structure unit, one data processing unit may simply perform only an autonomous data processing function, while another processing unit may perform a basic data processing function or both of the basic data processing function and the autonomous data processing function. Or, all the processing units may perform two of the data processing functions.
In the present application, xe2x80x9coperationxe2x80x9d in a data processing unit can be replaced with xe2x80x9cprocessingxe2x80x9d, and is rather a wider concept than processing, in the point of including, needless to say, basic logic operations represented by inversion, exclusive OR, OR, and AND, and an identity logic operation. The identity logic operation circuitoperation processing which outputs inputted data substantially or finally unchanged. Therefore, simple transfer of data is included in the identity logic operation. The identity operation is useful when data stored in a memory and outputted to the outside is reproduced later. In addition, for example, a case where the frequency of a reference clock supplied from the outside or a clock circuit in a data processing structure is changed or delayed by another clock circuit included in the data processing unit is equivalent to performance of a kind of xe2x80x9cprocessingxe2x80x9d on an input signal on the time axis, and therefore, this kind of frequency-dividing processing is included in the concept of xe2x80x9coperationxe2x80x9d.
The selector for selecting an appropriate one of the plurality of logic operations described above may be a circuit which performs the selection by a selection command supplied from the outside, in consideration of the physical request for downsizing of the area of the data processing unit, like the controller described above. In this case, the xe2x80x9coutsidexe2x80x9d may be an internal section or an external section of the data processing structure including the processing unit, like in the case of the controller described above. In addition, an embodiment of the selector may be a selection circuit incorporated in the data processing structure, which is controlled by a signal supplied from the outside of the data processing structure including the data processing unit and supplies a selection command to a selection gate.
Electric connection between a data processing unit and the outside can be realized by a connection between the input of the data processing unit and the outside. Electric connection between processing units in a polymer-like data processing structure unit can be realized by a connection between the input of one processing unit and the output of another processing unit or the output of the one processing unit itself. Further, in consideration of the physical request for the connection, the request for downsizing of the data processing structure, the request from operation speeds, and other requests from design matters, it is preferred that a polymer-like data processing structure unit between adjacent data processing units, and desirably, between data processing units arranged closest to each other.
In addition, from the idea of xe2x80x9cpolymerxe2x80x9d in data processing, it is possible to realize higher dispersed data processing. For example, when a logic operation too complicated for an operation in one single data processing unit is desired, a plurality of element operations required for the logic operation are assigned to two or more data processing units constituting a polymer-like data processing structure unit, and the logic operation can be performed by the entire polymer. Thus, it is possible to greatly enhance the flexibility and degree of freedom of design of dispersed data processing by the new idea according to the present invention.
In addition, in the case where a part of a polymer-like data processing unit does not comprise a write/read circuit but performs only an autonomous data processing function and the rest of the data processing unit performs both an autonomous data processing function and a basic data processing function, regions may be image-fixed respectively for the functions. Therefore, design can be performed for every region in a first stage of circuit design, and electric connection between regions can be designed in a subsequent second stage, so that the flexibility and degree of freedom of design of dispersed data processing can be greatly enhanced.
In addition, it is needless to say that the present invention does not exclude a case where the data processing units and the like are formed by quantum elements but can be practiced with equal functions and advantages in case where the units and the like are formed by quantum elements.
In the present invention, an embodiment which is not more commercial is not excluded. However, a more actual embodiment according to the present invention is, for example, a case where an array of memory cells is constructed by providing data processing units at cross-positions between a plurality of bit lines and a plurality of word lines. In this memory cell array, each memory cell performs a basic data processing function, i.e., each memory cell can perform writing or storing and reading or outputting of data by designation of an address through a bit line and a word line, and can also perform an autonomous data processing function as a feature of the present invention. That is, it is possible to exchange memory data between each memory cell and another memory cell, to perform operation processing on received data, and to store again an operation result thereof in place of data stored originally or store again the data stored originally itself, so that the operation result can be outputted when the memory cell is designated later.
In a two-dimensional memory cell array in which a bit line and a word line cross each other, there are normally two to four memory cells arranged closest to a particular memory cell, and there are normally eight or more memory cells adjacent to the particular memory cell. In a memory cell array in which memory cells are arranged three-dimensionally, it is apparent that the number of memory cells closest or adjacent to a particular memory cell is more than that in a case of a normal two-dimensional arrangement. As an actual problem, the difference between the xe2x80x9cclosestxe2x80x9d and xe2x80x9cadjacentxe2x80x9d will be determined individually in accordance with specific arrangements of a plurality of memory cells in a specific memory cell array. The data processing unit, data processing structure unit, and data processing structure according to the present is invention can respectively be considered as a memory cell, memory cell array, and memory device, although they are not limited thereto. Likewise, the concept of the xe2x80x9cclosestxe2x80x9d and the xe2x80x9cadjacentxe2x80x9d and the difference therebetween can be considered with reference to the case of the memory cell, memory cell array, and memory device.
In case where a data processing structure represented by a semiconductor memory device comprising the memory cell array includes a plurality of data processing structure units, these data processing structure units can be electrically connected with each other so that data can be transferred therebetween. The connection between the data processing structure units is provided for the same object as that of the connection between processing units in a polymer-like data processing structure unit. That is, for example, in case where the load of operation processing is too large for one single data processing structure unit, the processing elements constituting the operation processing are assigned to the plurality of data processing structure units and to one or two or more data processing units constituting each of the plurality of structure units, and the aimed operation processing can be performed by the entire polymer. Therefore, as this example means, the idea of connection between structure units enables enhancement of the flexibility and degree of freedom of design of a dispersed data processing. Note that it is also preferred to make electric connection between data processing structure units arranged adjacent to each other or desirably arranged closed to each other in consideration of the physical request for connection, the request for downsizing of the data processing structure, the request from operation processing, and other requests from design matters.